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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
* The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications * The IC06 74HC/HCT/HCU/HCMOS Logic Package Information * The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT7731 Quad 64-bit static shift register
Product specification File under Integrated Circuits, IC06 September 1993
Philips Semiconductors
Product specification
Quad 64-bit static shift register
FEATURES * Frequency range DC to 100 MHz. * Separate serial data inputs * Cascadable * Functionally compatible with HEF 4731 * Includes recycling mode * Direct shift out * Output capability: Standard * ICC category: LSI. APPLICATIONS * Data storage * Delay line. GENERAL DESCRIPTION The HC/HCT7731 are high-speed Si-gate CMOS devices. They are specified in compliance with JEDEC standard no. 7A. The HC/HCT7731 are quad 64-bit static shift registers with a recycling mode. Each register has separate data inputs Da to Dd, clock inputs CPa to CPd and data outputs Qa to Qd. Data shifts one place towards the output, each LOW to HIGH transition of the clock pulse. Each recycling mode input controls two registers RECab for registers A and B and RECcd for registers C and D. When the REC input is HIGH, the device is in the recycling mode and data at the output is shifted back into the input of the register, so after 64 clock pulses the contents of a register is again in its original position. This enables the user to tap off data from any position. When the REC input is LOW external data can be shifted in. CI CPD Notes QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns.
74HC/HCT7731
TYP. SYMBOL tPHL/tPLH fmax PARAMETER propagation delay CPa-d to Qa-d maximum clock frequency input capacitance power dissipation capacitance per register notes 1, 2 and 3 CONDITIONS HC CL = 15 pF; VCC = 5 V 15 HCT 20 ns MHz pF pF UNIT
100 100 3.5 58 3.5 61
1. CPD is used to determine the dynamic power dissipation (PD in W): PD = (CPD x VCC2 x fi) + (CL + VCC2 x fo) + (Ipull-up x VCC) where: fi = input frequency in MHz. fo = output frequency in MHz. VCC = supply voltage in V. CL = output load capacitance in pF. Ipull-up = pull-up currents in A. 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V. 3. See also power dissipation information. ORDERING INFORMATION EXTENDED TYPE NUMBER 74HC/HCT7731N 74HC/HCT7731D PACKAGE PINS 16 16 PIN POSITION DIL SO16 MATERIAL plastic plastic CODE SOT38Z SOT109A
September 1993
2
Philips Semiconductors
Product specification
Quad 64-bit static shift register
PINNING SYMBOL Qa to Qd CPa to CPd Da to Dd RECab, RECcd GND VCC PIN 1, 7, 9, 15 2, 6, 10, 14 3, 5, 11, 13 4, 12 8 16 DESCRIPTION data outputs clock inputs data inputs recycled enable input ground (0 V) positive supply
handbook, halfpage
74HC/HCT7731
Qa CP a Da REC ab Db CP b Qb GND
1 2 3 4
16 VCC 15 Q d 14 13 CP d Dd
7731
5 6 7 8
MBA341
12 RECcd 11 D c 10 9 CP c Qc
Fig.1 Pin configuration.
handbook, full pagewidth
3 Da 2 CP a 4 REC ab 5 Db 6 CP b
MUX
64 - BIT STATIC SHIFT REGISTER
Qa
1
MUX
64 - BIT STATIC SHIFT REGISTER
Qb 7
11 D c 10 CP c 12 RECcd 13 D d 14 CP d
MUX
64 - BIT STATIC SHIFT REGISTER
Qc
9
MUX
64 - BIT STATIC SHIFT REGISTER
Q d 15
MBA342
Fig.2 Functional diagram.
September 1993
3
Philips Semiconductors
Product specification
Quad 64-bit static shift register
74HC/HCT7731
handbook, full pagewidth
REC n D Dn Q FF1 CP D Q D Q Qn FF2 CP FF64 CP
MBA345
CP n to second shift register
Fig.3 Logic diagram.
FUNCTION TABLE INPUT REC L H Notes 1. L = LOW voltage level H = HIGH voltage Level = LOW-to-HIGH CP transition CP OUTPUT MODE shift recycle
September 1993
4
Philips Semiconductors
Product specification
Quad 64-bit static shift register
DC CHARACTERISTICS FOR 74HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: LSI. AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF. Tamb (C) SYMBOL PARAMETER MIN tPHL/tPLH propagation delay time CP to Qn - - - +25 TYP 50 18 15 19 7 6 19 7 6 8 3 3 22 8 7 -3 -1 -1 -8 -3 -3 26 78 93 MAX 155 31 26 75 15 13 - - - - - - - - - - - - - - - - - - -40 to +85 MIN - - - - - - 100 20 17 75 15 13 90 18 15 30 6 5 10 2 2 4.8 24 28 MAX 190 38 32 90 18 15 - - - - - - - - - - - - - - - - - - -40 to +125 MIN - - - - - - 120 24 20 90 18 15 110 22 19 35 7 6 15 3 3 4 20 23 MAX 230 46 39 110 22 19 - - - - - - - - - - - - - - - - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHZ MHz UNIT
74HC/HCT7731
TEST CONDITION VCC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 WAVEFORMS Fig.4
tTHL/tTLH
output transition - time - - clock pulse width HIGH or LOW set-up time Dn to CPn set-up time RECn to CPn hold time Dn to CPn hold time RECn to CPn 80 16 14 60 12 10 75 15 13 25 5 4 10 2 2
Fig.4
tW
Fig.4
tsu
Fig.4
tsu
Fig.5
th
Fig.4
th
Fig.5
fmax
maximum clock 6 pulse frequency 30 35
Fig.4 (note 1)
Note 1. The maximum power dissipation has to be observed. See power dissipation information.
September 1993
5
Philips Semiconductors
Product specification
Quad 64-bit static shift register
UNIT LOAD COEFFICIENT INPUT CPn RECn Dn Notes 1. The RS input has CMOS input switching levels. UNIT LOAD COEFFICIENT 0.7 0.4 0.5
74HC/HCT7731
2. The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications. To determine ICC per input, multiply this value by the unit load coefficient shown in Table 1. AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF. Tamb (C) SYMBOL PARAMETER - - 16 12 15 5 2 30 +25 MIN TYP tPHL/tPLH tTHL/tTLH tW tsu tsu th th fmax propagation delay time CP to Qn output transmission time clock pulse width HIGH or LOW set-up time Dn to CPn set-up time RECn to CPn hold time Dn to CPn hold time RECn to CPn maximum clock pulse frequency 24 7 7 3 6 0 -3 80 -40 to +85 -40 to +125 UNIT MAX MIN MAX 42 15 - - - - - - - - 20 15 18 6 2 24 52 18 - - - - - - MIN - - 24 18 22 7 3 20 MAX 63 22 - - - - - - ns ns ns ns ns ns ns MHz TEST CONDITION VCC (V) 4.5 4.5 4.5 4.5 2 2 4.5 4.5 WAVEFORMS Fig.4 Fig.4 Fig.4 Fig.4 Fig.5 Fig.4 Fig.5 Fig.4 (note 1)
September 1993
6
Philips Semiconductors
Product specification
Quad 64-bit static shift register
AC WAVEFORMS
74HC/HCT7731
handbook, full pagewidth
1/ f max
CPn INPUT
V M (1) tW tsu th tsu th
Dn INPUT
V M (1) t PLH V M (1) t TLH t THL t PHL
Q n OUTPUT
MBA320
(1) HC : VM = 50%; VI = GND to VCC HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.4
Waveforms showing the clock (CP) and data (D) input to output (Q) propagation delay, set-up, hold and transition times.
handbook, full pagewidth
1/ f max
CPn INPUT
V M (1) tW t su th t su th
REC n INPUT
V M (1)
MBA321
(1) HC : VM = 50%; VI = GND to VCC HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.5 Waveforms showing the clock (CP) to recycle (REC) set-up and hold times.
September 1993
7
Philips Semiconductors
Product specification
Quad 64-bit static shift register
74HC/HCT7731
POWER DISSIPATION INFORMATION The power dissipation per register operating at the same frequency is given by: PD = (CPD x VCC2 x fi) + (CL + VCC2 x fo) + (Ipull-up x VCC)
handbook, halfpage
60
MLA166
fi fo CL VCC
= clock input frequency = data output frequency = output load capacitance in pF = power supply voltage in V.
CPD (pF)
40
20
As PD also depends on the frequency at which the contents of the internal bits are changing, the value of CPD is a function of the duty factor (df) being the ration between data and clock frequency, see Fig.6. Example:
0 0 0.2 0.4 duty factor 0.6
fi fo CL VCC df CPD
= 12 MHz = 3 MHz = 25 pF =5V = 3/12 = 0.25 = 42.5 pF
Fig.6 CPD as a function of the duty factor.
PD = (42.5 x 52 x 12) + (25 x 52 x 3) = 14625 W As the maximum allowable power dissipation in an SO package at Tamb = 125 C is 60 mW, it is allowed to apply 4 registers at the same time under these conditions. PACKAGE OUTLINES See "74HC/HCT/HCU/HCMOS Logic Package Outlines".
September 1993
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